In general, a flash memory cell of a flash memory device may have a structure that includes a control gate, a coupling oxide, a floating gate and a tunnel oxide on a semiconductor substrate. The flash memory cell may be designed so that a positive voltage applied to the control gate may be coupled to the floating gate through the coupling oxide layer, and electrons in the semiconductor substrate may pass through the tunnel oxide layer by a Fowler-Nordheim (hereinafter, referred to as “F-N”) tunneling and may be captured in the floating gate. The flash memory cell may be erased by applying a positive voltage to the semiconductor substrate that causes the electrons in the floating gate to return to the semiconductor substrate by F-N tunneling.
A string of serially connected flash memory cells can be connected to a bit line for serially reading data from the flash memory cells or writing data to the flash memory cells. Since this control gate may be connected to several flash memory cells along a row orthogonal to the bit line for one or more words, it may be referred to as a word line. During a write operation of the flash memory cell, a program voltage on the control gate may enable transmission of data from the bit line or an adjacent flash memory cell into the flash memory cell. The coupling oxide layer, which is formed on the floating gate, may couple the program voltage applied to the control gate during a write operation to the floating gate so as to elevate the electric potential of the floating gate to create a write voltage between the floating gate and the semiconductor substrate across the tunnel oxide.
The coupling ratio K is a factor that may determine the amount of write voltage applied across the tunneling oxide during a write operation. The write voltage (i.e., Vtunnel write) applied to the tunneling oxide layer during a write operation may be expressed as shown in Equation 1 below.Vtunnel write=Vfloating gate+Kwrite×Vbitline/adjacent cell  (1)Herein, Vfloating gate refers to a voltage applied to the floating gate due to a program voltage application, Kwrite is a coupling ratio during a write operation, Vbitline/adjacent cell is a bit line or adjacent flash memory cell programming voltage. The coupling ratio Kwrite for a write operation can be expressed as shown in Equation 2 below.Kwrite=1−Ctunnel/(Ccoupling+Cparasitic+Ctunnel)  (2)Herein, Ccoupling is the capacitance of the coupling oxide, Ctunnel is the capacitance of the tunnel oxide, and Cparasitic is the parasitic capacitance of oxide variations or anomalies at or adjacent to the edges of the of the tunnel oxide.
As the parasitic capacitance Cparasitic increases, the coupling ratio Kwrite for a write operation may decrease. A decrease in the coupling ratio Kwrite for a write operation, may reduce the write efficiency for transferring data from the bit line or an adjacent flash memory cell. Such a reduction in write efficiency may be compounded each time data is serially transferred along a string of serially connected flash memory cells that each have the same reduced write efficiency. Further, there can be variations of parasitic capacitance Cparasitic among the string of serially connected flash memory cells. To increase write efficiency, it may be desirable to reduce the parasitic capacitance Cparasitic of a flash memory cell. In a string of serially connected flash memory cells, the parasitic capacitance Cparasitic may be reduced in each of the flash memory cells in a string of serially connected flash memory cells to increase write efficiency. Further, it may be desirable for the parasitic capacitance Cparasitic in the flash memory cells of a string of serially connected flash memory cells to be relatively consistent across the string of serially connected flash memory cells. Hereinafter, a method of manufacturing a conventional electrically erasable programmable read only memory (EEPROM) will be described with reference to FIGS. 6a to 6d. 
FIGS. 6a to 6d are cross-sectional views illustrating a conventional method of fabricating a flash memory device. As shown in FIG. 6a, a semiconductor substrate 10 includes a cell region and a peripheral region. The semiconductor substrate 10 can be single crystal silicon. The cell region is for flash memory devices and selection circuitry devices for the flash memory devices. The peripheral region is for high voltage power devices, such as power buffers, and low voltage devices that support both the selection circuits and the flash memory cells of the cell region.
The conventional method of fabricating a flash memory device illustrated in FIGS. 6a to 6d starts by forming a buffer oxide layer 12 in both the cell region and the peripheral region of the semiconductor substrate 10. Then, a hardmask layer 14 is formed on the buffer oxide layer 12 in both the cell region and the peripheral region of the semiconductor substrate 10. A mask (not shown) is then used to etch trenches 15 in both the cell region and the peripheral region through the hardmask layer 14 and the buffer oxide layer 12. Then, each of the trenches 15 and the openings in the hardmask layer 14 and in the buffer oxide layer 12 corresponding to each of the trenches 15 are filled with a dielectric, such as silicon dioxide, to form dielectric isolators 16. For increased electrical isolation between the high voltage devices of the peripheral region, the trenches 15 in the peripheral area can be wider and/or deeper than the trenches in the cell region.
As shown in FIG. 6b, active regions 17 are revealed in both the cell region and the peripheral region of the semiconductor substrate 10 by removing the hardmask layer 14 and the buffer oxide layer 12. The dielectric isolators 16 are in the trenches 15 and extend above the active regions 17 in the semiconductor substrate 10. The dielectric isolators 16 in the cell region have the same height as the dielectric isolators 16 in the peripheral region.
As shown in FIG. 6c, tunnel oxide layers 18a are then thermally grown on each of the active regions 17 in the cell region while gate oxide layers 18b are thermally grown on each of the active regions in the peripheral region. Subsequently, a conductive layer 20 is deposited over all of the cell region and the peripheral region, and onto the tunnel oxide layers 18a and the gate oxide layers 18b. Further, the conductive layer 20 fills the space between the dielectric isolators 16.
As shown in FIG. 6d, floating gates 20a are formed over the tunnel oxide layers 18a in the cell region while gate layers 20b are formed in the peripheral region by a chemical-mechanical polishing (CMP) process. More specifically, the conductive layer 20 shown in FIG. 6c is planarized to the top of the dielectric isolators 16 such that the conductive layer 20 is separated into floating gates 20a in the cell region and gate layers 20b in the peripheral region. Because of the increased width of the space between the dielectric isolators 16 in the peripheral region, there may be some dishing in the gate layers 20b from the CMP process.
FIG. 7 is a close-up cross-sectional view of a floating gate and a tunnel oxide grown by the related art method of fabricating illustrated in FIGS. 6a to 6d. As shown in FIG. 7, the tunnel oxide 18a is thinner near the edge of active region 17, as shown in region E1 of FIG. 7. This thinning effect may be caused by the thermal growth of the tunnel oxide 18a being suppressed at the edges of the tunnel oxide 18a because the edges of the tunnel oxide 18a are adjacent to the dielectric isolators 16. The amount of the thinning effect may not be the same for each flash memory cell of a string of flash memory cells. In other words, the thinning effect may not be consistent along a string of serially connected flash memory cells. Thus, the thinning effect may cause variations in parasitic capacitance Cparasitic in the flash memory cells along a string of serially connected flash memory cells. Further, the thinning effect may cause electric field focusing at the bottom edges of the floating gates 20a. Such electric field focusing causes further variations in the parasitic capacitance Cparasitic in the flash memory cells along a string of serially connected flash memory cells.
FIG. 8 is a close-up cross-sectional view of a floating gate and a tunnel oxide of another conventional method of fabricating a flash memory device. The other conventional method of fabricating a flash memory device starts by thermally growing a tunnel oxide layer over the entire surface of the semiconductor substrate 10 in both the cell region and the peripheral region of the semiconductor substrate. Then, a conductive layer is formed on the tunnel oxide layer in both the cell region and the peripheral region of the semiconductor substrate 10. A mask is then used to etch trenches 15 in both the cell region and the peripheral region through the conductive layer and the tunnel oxide layer to form a gate layer 20c on a tunnel oxide layer 18c above an active region 17. Such a fabrication method is known as a self-aligned trench isolation method.
The thinning effect at the edges of the tunnel oxide layer 18c does not occur in a self-aligned trench isolation method. However, the edges of the tunnel oxide layer 18c tend to be thicker than a center portion of the tunnel oxide layer 18c, as shown in region E2 of FIG. 8. This thickening at the edges of the tunnel oxide layer 18c may occur during a repair processing to repair dry etch damage caused by the etching of the trenches 15 and to round the edges of the active regions 17 to prevent stress defects in the active regions 17 of both the cell region and the peripheral region. The repair processing may grow thin oxide layers on the semiconductor substrate 10 in the trenches 15 and on the sides of the gate layer 20c. 
The gate layer 20c is made of polycrystalline silicon. The oxidation rate of polycrystalline silicon is greater than single crystal silicon. Because the gate layer 20c is made of polycrystalline silicon, the repair processing thickens the edges of the tunnel oxide layer 18c due to oxidation of the edges of the gate layer 20c adding to the thickness of the tunnel oxide layer 18c at the edges of the tunnel oxide layer 18c. 
The thickened edges of the tunnel oxide layer 18c may increase the parasitic capacitance Cparasitic of the flash memory cell. Further, the thickened edges of the tunnel oxide layer 18c may prevent shrinkage of the design rules for obtaining a functional tunneling oxide layer.